After the conversion by ADC, data (1024 bytes/event) are sent through a FIFO to an 8 channel bus interface with
D2. Here all tasks of event processing are performed, before sending
the data to E for mass memory storage.
All the procedures of acquisition, data handling and telecommands are executed by this subsystem.
The core of D2 are two 8086 microprocessors working with a clock speed of 4 MHz. In normal conditions both of them are operating in Master-Slave mode: the Master microprocessor receives the event from D1 and performs pedestal suppression and data reduction tasks, while the Slave is used to format the data, according to the acquisition mode, and send them to E. It also selects the trigger logic, implements the Second Level trigger and interfaces most of the telecommands with D1.
This redundant architecture allows the system to work with a maximum acquisition speed of 100 Hz. In case of failure of one of the two 8086, all tasks can be performed - at a reduced speed (about 70 Hz) - by the remaining one (Figure 1).
The on-board software, written in Assembler, is placed on EPROM; there are some RAM banks memory common to both the processors. The communications in input from D1 and output to E are realized through two FIFO redundant systems. The D1 status (thresholds, selected trigger, ...) takes an independent line. Other inputs are represented by the telecommand status which determines the operating mode of the D2 system. At the switching ON of the system, the program starts executing and checks the status of the two processors: if both are ON, they start working in the normal Master-Slave mode, otherwise only one of the two will perform all D2 tasks.